This invention relates to semiconductor packaging.
Portable electronic products such as mobile phones, mobile computing, and various consumer products require higher semiconductor functionality and performance in a limited footprint and minimal thickness and weight at the lowest cost. This has driven the industry to increase integration on the individual semiconductor chips, and also to implement integration on the “z-axis,” that is, by stacking chips or by stacking die packages to form a stacked package assembly (stacked multi-package module).
Stacked package assemblies are employed in applications in which there is a need to provide a high degree of functional integration in an assembly having a minimal footprint and thickness. Portable telecommunications devices such as cellular telephones are an example of such applications, particularly where the telecommunications device includes, for example, capabilities for capture and display or play of images, audio or video.
Examples of functions that may desirably be integrated include devices for: various processes, including digital signal (DSP), ASIC, graphics (GPU); various memories, including Flash (NAND), Flash (NOR), SRAM, DRAM, MRAM; image and video capture, including optical sensor with memory; micro-electro-mechanical systems (MEMS) with processor and memory.
The z-interconnect between packages in a stacked package assembly is a critical technology from the standpoint of manufacturability, design flexibility and cost. Stacked package assemblies integrate chips and packages by stacking and electrically interconnecting them in the z-direction using wire bonds, or solder balls, or flip chip interconnection.
Stacked packages can provide numerous advantages. Particularly, each die or more than one die can be packaged in a respective package in the stack using the most efficient first level interconnect technology for the chip type and configuration, such as wire bonding or flip chip, to maximize performance and minimize cost.
It is desirable to be able to electrically test the stacked components (die or packages), so that the component can be rejected unless it shows satisfactory performance, before the packages are stacked. This permits maximizing the yield of the final stacked package assembly. To realize this advantage in practice, the packages must be configured to be testable using established test infrastructure. Generally, testing packaged die is preferable to testing individual die, as testing individual die can result in damage to interconnection pads on the die.
Often, the manufacturer of a product (particularly for example where the product is a portable communications device such as a cellular phone) determines the dimensions of a space in which the assembly must fit. That, is the manufacturer will demand that an assembly having specified functionalities have an overall footprint (length and width) and thickness within particular specifications. Presented with such limitations, the designer must, within cost limitations, be able to select packages and a stacking design and process that meet the demands for functionality within the limitations of thickness and footprint.
Accordingly, it is desirable to choose a multi-package stack structure and stacking process that provides design flexibility for the function designer. Particularly, for example, the designer should have flexibility, without having to redesign the structure or the process: to choose packages or chips from any of a variety of available vendors, to minimize component cost; to make changes in chip or package types within the assembly, to avoid having to re-qualify a changed assembly; and to complete the assembly stacking process at the final product stage on the surface mount assembly floor, to enable product configurations demanded by the market in the shortest practical time-to-market.
Meeting rapidly changing market demands can present challenges. For example, the general timeframe for designing a consumer device such as a cellular phone is typically longer than the timeframe for market shifts. A perception may develop in the industry that a particular functionality is desirable in a consumer device (e.g., web browsing functionality in a cellular phone), and designers may build that functionality into the assemblies; then within a short time it may become evident that the demand in the marketplace is not as had been perceived, and it may be desirable to remove that functionality or to present it in the marketplace as an option. Accordingly, it is desirable to be able to configure the device “on the fly”, that is, to add or remove functionalities in a device without having to redesign the entire assembly.
It is desirable also to be able to stack off-the-shelf packaged chips, such as for example memory (Flash, SRAM, DRAM), over other packages in the assembly, using surface mount assembly methods employed in the industry for assembling products such as mobile communications devices (e.g., cellular phones) and computers. The type of memory for a product, in particular, can be different for different functionalities; for instance, if image capture functionality is desired in a cellular phone, a fast memory (DRAM) may be required.
The packages employed in stacked package assemblies and the manufacturing processes must be configured to enable both the physical stacking of the packages and the formation of electrical interconnections between them, using a chosen process for a chosen structure.
Stacked multi-package assemblies generally fall into two categories, namely, so-called “Package-on-Package” (PoP) assemblies, and so-called “Package-in-Package” (PiP) assemblies.
Examples of 2-stack PoP multi-package modules are shown for example in copending U.S. application Ser. No. 10/681,572, filed Oct. 8, 2003. In one example a first package (referred to as the “bottom” package) is similar to a standard BGA, having a die affixed to and electrically connected with the die attach side (the “upper” side) of a BGA substrate, and being cavity molded to provide a mold cap covering the die and electrical connections but leaving a marginal area of the die attach side of the substrate exposed. The side of the bottom package substrate opposite the die attach side (the “lower” side, which may be referred to as the “land” side) is provided with solder balls for second level interconnection of the module with underlying circuitry such as, for example, a motherboard. A second package (referred to as the “top” package) is stacked on the bottom package and is also similar to a standard BGA, except that the solder balls provided on the land side of the top package are arranged at the periphery of the top package substrate, so that they rest upon interconnection sites at the exposed marginal area of the die attach side of the bottom package. When the peripherally arranged balls are contacted with and then reflowed onto the peripherally located interconnect sites at the bottom package, they effect the z-interconnection without interference with the mold cap of the bottom BGA. The top package die and electrical connections are also encapsulated.
The type of z-interconnect employed in the PoP module requires that the top and bottom package substrates be designed with matching pads for the z-interconnect balls. If one of the packages is exchanged for one in which the substrate has a different pad arrangement (different size or different design), then the substrate for the other package must be reconfigured accordingly. This leads to increased cost for manufacture of the multi-package module. In the PoP configuration the distance between the top and bottom packages must be at least as great as the encapsulation height of the bottom package, which may be 0.25 mm or more, and typically is in a range between 0.5 mm and 1.5 mm, depending upon the number of die and depending upon whether the die-to-substrate electrical connection is by flip chip or by wire bonds. For example, for a single wire bonded die in the bottom package a moldcap of 300 um can typically accommodate a 75 um thick die. The z-interconnect solder balls must accordingly be of a sufficiently large diameter that when they are reflowed they make good contact with the bonding pads of the bottom BGA, without contact between the land side of the top package substrate and the upper surface of the bottom package mold cap; that is, the solder ball diameter must be greater than the encapsulation height by an amount that allows for solder ball collapse during reflow, plus a tolerance for noncoplanarities between balls and substrate. A typical design difference (additional clearance) between collapsed ball height and bottom mold cap height is about 25 um. For a moldcap having a thickness about 300 um, for example, z-interconnect solder balls greater than 300 um must be employed. A larger ball diameter dictates a larger ball pitch (typically about 0.65 mm pitch for 300 um balls, for example). That in turn limits the number of balls that can be fitted in the available space in the periphery of the bottom package substrate. Furthermore the peripheral arrangement of the solder balls forces the bottom BGA to be significantly larger than the mold cap of a standard BGA. And the peripheral arrangement of the solder balls increases the overall package size (the size increases according to the number of ball rows and the ball pitch). In standard BGAs the body size can be as much as about 2-3 mm larger than the mold cap. Moreover, the top package in a PoP configuration must be made of comparable size to the bottom one even though it may contain a small chip with many fewer interconnects. Increasing package footprint, to provide greater area for ball attachment (additional rows of balls, for example), may exceed the size limits for the particular application, and in any event entails longer wire bond spans and greater substrate area, both of which increase the cost of these components. Increasing the numbers of interconnections between packages may require that the top package substrate have at least two metal layers (and often more than two) to facilitate the routing within the substrate electrical connections. It may in some applications be impractical in a PoP configuration to stack two die in the bottom package, as this causes the bottom mold cap to be even thicker, exacerbating the problems described above.
Examples of two-stack PiP modules, having z-interconnection by wire bonds between the upward-facing sides of the top and bottom package substrates, are disclosed for example in copending U.S. application Ser. No. 10/632,549, filed Aug. 2, 2003, and copending U.S. application Ser. No. 10/681,572, filed Oct. 8, 2003. In the PiP configuration, the top package may be either oriented in the same direction as the bottom package (that is, with the die attach sides of both package substrates facing the same direction); or the top package may be inverted with respect to the bottom package (that is, with the die attach sides of the respective package substrates facing one another). Second-level interconnect solder balls are provided on the land side of the bottom package substrate for connection of the module with underlying circuitry such as, for example, a motherboard. In configurations where the top package is inverted, the z-interconnection wire bonds connect wire bond sites at the land side of the top substrate with peripherally arranged wire bond sites on the die attach side of the bottom package substrate. Where the top and bottom packages are oriented the same way, the z-interconnection wire bonds connect peripherally arranged wire bond sites at the die attach side of the top substrate with peripherally arranged wire bond sites at the die attach side of the bottom package substrate. In both configurations, the top package must be smaller (narrower and/or shorter by at least 0.5 mm on each margin that has z-interconnections) than the bottom package to accommodate the wire bond process.
The PoP module or PiP module is completed by overmolding, to entirely cover the top package and the wire bond interconnects between the packages. Once the module has been overmolded, no further integration can be made. That is, the designer has no flexibility to reconfigure the assembly at the product assembly level (that is, at the surface mount assembly floor); and the original equipment manufacturer cannot mix-and-match various packages from various suppliers to reduce costs.